The present invention relates to solid-state imaging apparatus, and more particularly relates to a solid-state imaging apparatus which is capable of suppressing level difference between a black reference level value by a reference potential readout and a black level value of an effective pixel section.
It has conventionally been necessary to correct output variance among pixels when image is to be taken with using a solid-state imaging apparatus. For this reason, a correlation double sampling (hereinafter referred to as CDS) is effected. Further, it is necessary to subtract an error signal (dark current component) due to dark current from an image signal to bring a black level of image signal to a certain level, and a pixel shielded from light (optical black; hereinafter, abbreviated as OB) is referred to so as to detect such dark current component.
In the case where a scene of extremely high luminance throughout or scene containing a high-luminance point light source such as a spot light is to be taken, however, OB signal level may vary and, if a black level correction is effected with using the varied OB signal, a failure in image signal occurs as a consequence.
A proposal has been made in Japanese Patent Application Laid-Open 2004-320346 to solve this problem. FIG. 1 is a diagram showing construction of the solid-state imaging apparatus disclosed in Japanese Patent Application Laid-Open 2004-320346; and FIG. 2 is a timing chart for explaining its operation. The construction of the solid-state imaging apparatus disclosed in the publication will now be described by way of FIG. 1. Referring to FIG. 1, PIX11 to PIX33 denote pixels arranged into rows and columns (matrix arrangement). Of these pixels PIX11 to PIX33, the pixels PIX11 to PIX13 of the first column constitute a light-shielded pixel section 1 (reference pixel section), and the pixels PIX21 to PIX23, PIX31 to PIX33 of the second and third columns constitute an effective pixel section 2. The surface of each pixel of the light-shielded pixel section 1 is covered with such light-shielding film as aluminum.
The pixels PIX11 to PIX33 of the light-shielded pixel section 1 and effective pixel section 2 each include: a photodiode D11 to D33; a transfer MOS transistor M111 to M133 for transferring electric charge of the photodiode D11 to D33; a reset MOS transistor M211 to M233 for resetting the transferred electric charge; an amplification MOS transistor M311 to M333 for amplifying electric charge of the photodiode D11 to D33; and a select MOS transistor M411 to M433 for selecting pixels arranged in a row direction.
Further, gate of the reset MOS transistor M211 of the pixel PIX11 is connected to a reset control line φRS1 disposed in a manner extended in a row direction. The gates of reset MOS transistors (M221, M231) of the other pixel cells (PIX21, PIX31) disposed in the same row are also connected in common to the same reset control line φRS1. The gate of the transfer MOS transistor M111 of PIX11 is connected to a PD signal transfer control line φTR1 disposed in a manner extended in the row direction. The gates of the transfer MOS transistors (M121, M131) of the other pixel cells (PIX21, PIX31) disposed in the same row are also connected to the same PD signal transfer control line φTR1. The gate of the select MOS transistor M411 of PIX11 is connected to a row select control line φSEL1 disposed in a manner extended in the row direction. The gates of the select MOS transistors (M421, M431) of the other pixel cells (PIX21, PIX31) disposed in the same row are also connected to the same row select control line φSEL1. Also to the pixels of the second row consisting of the pixels PIX12 to PIX32, a reset line φRS2, PD signal transfer control line φTR2, and row select control line φSEL2 are connected, and a reset control line φRS3, PD signal transfer control line φTR3, and row select control line φSEL3 are connected to the pixels of the third row consisting of the pixel PIX13 to pixel PIX33. These reset control lines φRS1 to φRS3, PD signal transfer control lines φTR1 to φTR3, and row select control lines φSEL1 to φSEL3 are respectively connected to a vertical scanning circuit 3, and signal voltages are supplied from the vertical scanning circuit 3 so that each section of each pixel is driven/controlled.
Further, reference symbols V1 to V3 respectively indicate vertical signal lines for extracting output signal of the amplification MOS transistors M311 to M313, M321 to M323, and M331 to M333 of the pixels arranged in each column. Reference symbols I41 to I43 respectively indicate current sources for biasing the vertical signal lines V1 to V3. A noise suppressing circuit 4 includes clamping capacitors CCL1 to CCL3 that are connected to the respective vertical signal lines V1 to V3, sample-and-hold switches M11 to M13, clamp switches M21 to M23, and sample-and-hold capacitors CSH1 to CSH3. The noise suppressing circuit 4 is to accumulate amplitude components of the vertical signal lines V1 to V3. Further, M31 to M33 each are a horizontal select switch for selecting/outputting output signal of the noise suppressing circuit 4; 5 is a horizontal scanning circuit for driving the horizontal select switches M31 to M33; and 6 is an output amplifier. It should be noted that a predetermined control of the vertical scanning circuit 3, horizontal scanning circuit 5 and noise suppressing circuit 4 is effected by control signal from a control section 10.
A signal read operation of the effective pixel PIX21 in the solid-state imaging apparatus shown in FIG. 1 will now be described by way of a timing chart shown in FIG. 2. At first, before reading electric charge of light signal of the photodiode D21, the reset control line φRS1 and row select line φSEL1 are driven to high level. The gate of the amplification MOS transistor M321 is thereby reset to a pixel power supply 7. Further, the sample-and-hold control line φSH and clamp control line φCL1 are driven to high level. The sampling capacitor CHS2 and clamp capacitor CCL2 are thereby initialized to the potential of a clamp voltage line 8.
Next, the reset control line φRS1 is set to low level. The pixel power supply line 7 can be thereby disconnected from the gate of the amplification MOS transistor M321. Subsequently, the clamp control line φCL1 is brought to low level so as to accumulate reset signal component of the effective pixel PIX21 to the clamp capacitor CCL2. At this time, a connecting point (sample-and-hold line) VSH2 between the sample capacitor CSH2 and the clamp switch M22 is brought into a high-impedance state.
Subsequently, PD signal transfer control line φTR1 is driven to high level so as to transfer a light signal electric charge of the photodiode D21 to the gate of the amplification MOS transistor M321. The PD signal transfer control line φTR1 is then brought to low level to disconnect the photodiode D21 and the gate of the amplification OS transistor M321 from each other.
At this timing, a potential change or a difference voltage between the reset signal component and the light signal component occurring on the vertical line V2 is accumulated at the sample-and-hold capacitor CSH2 through the clamp capacitor CCL2 and sample-and-hold switch M12. Subsequently, the sample-and-hold control line φSH is brought to low level so that signal component of the effective pixel PIX21 is retained at the sample-and-hold capacitor CSH2.
A reference signal read operation associated with the light-shielded pixel PIX11 will now be described. The operation up to the initialization of the clamp capacitor CCL1 and the sampling capacitor CSH1 to the potential of the clamp voltage line 8 by operating the clamp control line φCL2 and the clamp control line φCL1 at the same timing is identical to that of the effective pixel PIX21 and will not be described. Now, after the initialization of the clamp capacitor CCL1 and sampling capacitor CSH1 to the potential of the clamp voltage line 8, the reset control line φRS1 is set to low level. The pixel power supply line 7 can be thereby disconnected from the gate of the amplification MOS transistor M311. At this time, the clamp control line φCL2 retains high level, and terminal potentials of the clamp capacitor CCL1 and the sample-and-hold capacitor CSH1 remain to be fixed to the potential of the clamp voltage line 8.
Subsequently, PD signal transfer control line φTR1 is driven to high level to transfer a light signal electric charge of the photodiode D11 to the gate of the amplification MOS transistor M311. The PD signal transfer control line φTR1 is then brought to low level to disconnect the photodiode D11 from the gate of the amplification MOS transistor M311.
Subsequently, while the sample-and-hold control line φSH is brought to low level, clamp control line φCL2 is kept to high level. The terminal potentials of the clamp capacitor CCL1 and sample-and-hold capacitor CSH1 thereby remain to be fixed to the potential of the clamp voltage line 8. Finally, the clamp control line φCL2 is brought to low level so that a signal VSH1 sampled at the sampling capacitor CSH1 is brought to the potential of the clamp voltage line 8.
It should be noted that, in FIG. 2, VNφCSH1 is a noise resulting from feedthrough components occurring on the sample-and-hold line VSH1 when reference signal associated with the light-shielded pixel PIX11 is read out, which is consisting of the noise resulting from the feedthrough component due to gate-source overlap capacitance of the clamp switch M21. Further, VNφCSH2 is a noise resulting from feedthrough components occurring on the sample-and-hold line VSH2 when black level signal of the effective pixel PIX21 is read out, which is consisting of an addition of the noise resulting from the feedthrough component due to gate-source overlap capacitance of the clamp switch 22 and the noise resulting from the feedthrough component due to gate-source overlap capacitance of the sample-and-hold switch M12.